Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Carriy Routing VHDL How?

I have a piece of VHDL which renders to 299 LEs MAX II,and quartus 8.0detects the (carry) chain of a and/xor impleented full adder, with extra contol signals to select just the xr part, te and shifte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

From your post, I can't see clearly that the router is performing poor with the said design, particularly wasting resources. Can you give a minimal code example that illustrates your request?