Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- Introdution: The Quartus gives a netlist file like output file. This file contain information about resistors, transistors, capacitors, etc. --- Quote End --- The assumption is wrong. The Quartus netlist file represents the synthesiszed logic in terms of LE (logical elements) and their interconnection. Transistor level netlists aren't generated by any FPGA synthesis tool neither Altera Quartus nor any other vendor's tool. The information you want isn't available for FPGA.