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I don't understand this problem, just two days ago it didn't happen and now it does. What could be the problem?
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This looks like theres files missing in MODELSIM. I suggest driving modelsim yourself and not relying on Quartus to do this for you. The commands are very straightforward. If you have files a.vhd and b.vhd with the top level entity called "testbench" inside a.vhd, then all you need to do is this in the modelsim console:
vcom a.vhd
vcom b.vhd
vsim testbench
(use vlog instead of vcom for verilog files).
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Also, I would appreciate if you could tell me how to test internal signals of a BDF file in Modelsim using a testbench. I know that I can give the signals names, turn the BDF file into a HDL file and then compile it in Modelsim, and then force the signals, but I want to use a testbench to make this be automatic. Problem is, using a testbench, I only see the input/outputs.
Thank you!
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BDF files cannot be simulated, so you can only see what is in the generated HDL file. As for driving them, with verilog you can always force/drive any signal within the hierarchy. With VHDL this requires you to use VHDL 2008. But if you need to drive internal signals then I suggest you have a problem with the design - testbenches should only ever drive the DUT io. You can always monitor internal signals on the wave window or log them in your HDL.
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