Can't use 'numeric_std_unsigned' package in Quartus prime lite edition v15.1

I'm using quartus prime lite edition v15.1, trying to write a register file in vhdl. In my code i need to use ' numeric_std_unsigned' package, but an error pops up saying :

library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use IEEE.numeric_std_unsigned.all;
 entity regfile is
 port(        clk: in STD_LOGIC;
               regwrite: in STD_LOGIC;  
               rs, rt, rd: in STD_LOGIC_VECTOR(1 downto 0); 
               data_in: in STD_LOGIC_VECTOR(15 downto 0); 
              rd1, rd2: out STD_LOGIC_VECTOR(15 downto 0)); 
 end;
 architecture behave of regfile is type registerFile is
     array (3 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
     signal registers: registerFile;
 begin 
 process(clk) begin
    if rising_edge(clk) then 
       if regwrite='1' then
       registers(to_integer(rd)) <= data_in; 
       end if;
    end if;
 end process;
 
process(all)
 begin
      if (to_integer(rs)=0) 
        then rd1 <= X"0000"; 
          else rd1 <= registers(to_integer(rs)); 
     end if;
   if (to_integer(rt)=0) 
     then rd2 <= X"0000";
     else rd2 <= registers(to_integer(rt));
   end if;
 end process; 
end;