Can't Simulate Buffer port in ModelSim

Hello everyone, I have the following simple VHDL code for clock frequency division:

---------------------- Frequency division using Variables -------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

-----------------------------------------

ENTITY freq_divider IS

PORT ( clk : IN STD_LOGIC;

out2 : BUFFER STD_LOGIC);

END freq_divider;

-----------------------------------------

ARCHITECTURE example OF freq_divider IS

BEGIN

PROCESS (clk)

VARIABLE count2 : INTEGER RANGE 0 TO 7;

BEGIN

IF (clk'EVENT AND clk='0') THEN

count2 := count2 + 1;

IF (count2 = 3) THEN

out2 <= NOT out2;

count2 := 0;

END IF;

END IF;

END PROCESS;

END example;

-----------------------------------------

But when I try to Simulate it with modelsim-altera the (out2) signal does not give me any value. I was wondering is it because the port is assigned as (buffer)????? Please help me. Thanks