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Altera_Forum
Honored Contributor
18 years agoPerhaps it's my use of muxes? I'm trying to redo my 2:1 mux but I'm having trouble getting it to compile.
ARCHITECTURE Behavior OF VHDLMux21 IS
SIGNAL output : STD_LOGIC_VECTOR(15 downto 0);
PROCESS(a,b,s)
BEGIN
IF s = '0' THEN
output <= a;
ELSE
output <= b;
END IF;
END PROCESS;
c <= output;
END Behavior;