Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHello,
--- Quote Start --- Well now it seems like nothing is happening. Shifting right shifts the wrong amounts and shifting left doesn't work at all. --- Quote End --- according to Quartus timing simulation the code seems to work correct. May be you're operating it too fast? However, using a rotate function from numeric_std package, you get functional equivalent code that is somewhat shorter. Typecasts are needed cause the function isn't defined for std_logic_vector.library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- ....
ARCHITECTURE Structure OF Multi2 IS
BEGIN
aluOut <= std_logic_vector(ROTATE_LEFT(UNSIGNED(aluIn),
TO_INTEGER(UNSIGNED(shift)))) WHEN shiftRight = '0' else
std_logic_vector(ROTATE_RIGHT(UNSIGNED(aluIn),
TO_INTEGER(UNSIGNED(shift))));
END Structure; Interestingly, Quartus synthesis ignores the multiple steps in your code, collapsing it to an single bit rotation, thus both variants are requiring identical LE count and have identical timing. You can examine XROR and XROL definition in library numeric_std.vhd to see how bit rotation can be coded in a compact way. Regards, Frank