Can't resolve multiple constant drivers?

Well now it seems like nothing is happening. Shifting right shifts the wrong amounts and shifting left doesn't work at all.

ENTITY ShiftRegister IS
	PORT (aluIn : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		  shift : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--rotate amount
		  shiftRight : IN STD_LOGIC;--if 1, right, if 0, left
		  aluOut : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)--rotated output
		  ); 
END ShiftRegister;
ARCHITECTURE Structure OF ShiftRegister IS
SIGNAL alu1: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL alu2: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL alu3: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL tempL1: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL tempR1: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL tempL2: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL tempR2: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL tempL3: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL tempR3: STD_LOGIC_VECTOR(15 DOWNTO 0);
COMPONENT busmux4to1
PORT
(
	selectIn: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	a: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	b: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	c: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	d: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	e: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
BEGIN
--4 rotation
tempL1<=aluIn(11 DOWNTO 0) & aluIn(15 DOWNTO 12);
tempR1<=aluIn(3 DOWNTO 0) & aluIn(15 DOWNTO 4);
stage0: busmux4to1 PORT MAP(shiftRight & shift(2),aluIn,tempL1,aluIn,tempR1,alu1);
--2 rotation
tempL2<=alu1(13 DOWNTO 0) & alu1(15 DOWNTO 14);
tempR2<=alu1(1 DOWNTO 0) & alu1(15 DOWNTO 2);
stage1: busmux4to1 PORT MAP(shiftRight & shift(1),alu1,tempL2,alu1,tempR2,alu2);
--1 rotation
tempL3<=alu2(14 DOWNTO 0) & alu2(15);
tempR3<=alu2(0) & alu2(15 DOWNTO 1);
stage2: busmux4to1 PORT MAP(shiftRight & shift(0),alu2,tempL3,alu2,tempR3,alu3);
aluOut<=alu3;
END Structure;