Can't place multiple pins assigned JTAG shared pins

Hi,

For MAX 10 device, you only need to check chapter 3.1. Dual-Purpose Configuration Pins in MAX® 10 FPGA Configuration User Guide. This chapter didn't mention any actions you need to take in the "dual-purpose pin" tab.

As you can see from 3.1.1.1. JTAG Pin Sharing Behavior, when you enable " JTAG Pin Sharing" in the General tab:

• During Configuration, these pins are dedicated JTAG pins.
• During User mode, these pins can switch between dedicated JTAG pins and user I/O by control the JTAGEN signal.

As you can see these "altera_reserve_tms"... pins in Pin Planner, I think you have probably instantiated JTAG related ip in your design. This would be the major reason you see the error.

You can see the following Note in Table 25 of 3.1.1. Guidelines: Dual-Purpose Configuration Pin.

"The Signal Tap logic analyzer IP, JTAG-to- Avalon® master bridge IP, and other JTAG-related IPs cannot be used if you enable the JTAG pin sharing feature in your design."

For example, when I add In-system source and probe IP to my design, and I assign GPIO to TCK, the fitter will report the failure.

Best Regards,

Xiaoyan