Can't instantiate Signal Tap using megafunction tool in Quartus 17.0.1

Here is my code. I don't think it has anything to do with the instantiation because if I generate the IP as a Verilog module things work. Why do I get this error generating the IP core in VHDL?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity adder_top is

port(

clock : in std_logic;

resetn : in std_logic;

oready : out std_logic;

ivalid : in std_logic;

idata : in std_logic_vector(31 downto 0);

ovalid : out std_logic;

iready : in std_logic;

odout : out std_logic_vector(31 downto 0)

);

end adder_top;

architecture Behavioral of adder_top is

component signal_tap is

port (

acq_clk : in std_logic := 'X'; -- clk

acq_data_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- acq_data_in

acq_trigger_in : in std_logic_vector(0 downto 0) := (others => 'X') -- acq_trigger_in

);

end component signal_tap;

signal s_sum : unsigned(32 downto 0);

signal s_trigger : std_logic_vector(0 downto 0);

begin

ovalid <= '1';

odout <= std_logic_vector(s_sum(31 downto 0));

oready <= '1';

s_trigger(0) <= ivalid;

process(clock)

begin

if rising_edge(clock) then

if (resetn='0') then

s_sum <= (others=>'0');

else

s_sum <= s_sum + X"00000001";

end if;

end if;

end process;

signal_tap_inst : component signal_tap

port map (

acq_clk => clock,

acq_data_in => idata(31 downto 0) & std_logic_vector(s_sum(31 downto 0)),

acq_trigger_in => s_trigger

);

end Behavioral;