Can't inplement this code...Help!

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I need to inplement this code and than use it for another code:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

package ad_filt is

constant NUM_TAPS : integer := 16:

constant mu : integer := 16;

type sh_reg is array (0 to NUM_TAPS-1) of std_logic_vector(15 downto 0);

type tmp_reg is array (0 to NUM_TAPS-1) of std_logic_vector(31 downto 0);

end ad_filt;

I need to implement this code above.And after that to use it in another code with command:

use work.ad_filt.ALL;

When I try to inplement code above I have lots of errors...My English is bad so I have difficulty to explain.

Thanks Tricky...

Is there some tutorial where I can see how to 2,3,4 or more VHDL codes put in one quartus project?

Tomorrow I will put errors here,then you can see whats wrong...Thanks anyway!