Can't generate .vo file

Question

Hi,

My design includes a fir filter generated using fir_compiler 3.3.1.

I want to generate the .vo file of this design and do function simulation in modelsim.

When doing the complete compilation, analysis & synthesis, fitter ,assembler and classic timing analysis are all OK. But the EDA Netlist Writer fails and can't generate this .vo file . The error is " Can't generate netlist output files because the file "C:/altera/megacore/fir_compiler-v3.3.1/lib/tdl_da_lc.v" is an OpenCore Plus time-limited file".

How to solve it ?

Thanks!

Tigre

altera_forum · Answer

If this IP doesn't support try-before-you-buy simulation, then you have to pay for a license.  You can use the OpenCore .sof file to try out the IP in hardware without a license.

altera_forum · Answer

who knows the meaning of these equations which has been written in .vo file?

please help me. I have no idea about LCELL and CARRY!

\comp1|LessThan0~47COUT1_98 = CARRY(\A~combout [1] & \B~combout [1] & !\comp1|LessThan0~52COUT1_96 # !\A~combout [1] & (\B~combout [1]# !\comp1|LessThan0~52COUT1_96 ))

Thanks

altera_forum · Answer

The said LCELL and CARRY are the real gate-level entities used in Altera FPGAs. You can read a functional description in the designing with low-level primitives user guide http://www.altera.com/literature/ug/ug_low_level.pdf. The logic expressions are generic ABEL, their meaning is obvious to my opinion, cause ony NOT, AND, OR and XOR are used from of the ABEL operators.

altera_forum · Answer

HI,  where I can find the precedence of these operators?  Thanks

altera_forum · Answer

There are ABEL references at the internet. E.g. http://www.seas.upenn.edu/~ese201/abel/abel_primer.html

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Can't generate .vo file

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