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Altera_Forum's avatar
Altera_Forum
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17 years ago

Can't generate .vo file

Hi, My design includes a fir filter generated using fir_compiler 3.3.1. I want to generate the .vo file of this design and do function simulation in modelsim. When doing the complete...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Dear Fvm!,

Thanks for your very useful help. I have another question :)

Is there any way to extract the gate-level netlist of synthesized behavioral verilog code in Quartus or Xilinx ISE?

Thank U so much.