cant find the problem with my code

basically, i need the counter to be counting correct as i am trying to implement my code for ADC usage, which uses SPI and its vital that the counting cycle is correct. Thank you all.

How are you testing the design (Modelsim, Signaltap) and what do you exactly observe?

Unfortunately, I tried modelsim but without much help and mostly vague guides online, I can't seem to get it to work. Basically, I'm using the LED as an indication to over counting.

A ripple clock is a clock that is generated via logic - ie. exactly what you have done - used a counter to create a slower clock from a faster one. It is better practice to use the same clock over the whole system and generate clock enables to only enable the target at the given rate. So to divide a clock by 50, you create an enable signal that is high for 1 clock cycle in 50:

process(clk)
begin
  if rising_edge(clk) then
    if en = '1' then    --only high once every 50 clocks
      --logic with 1/50 clock
    end if;
  end if;
end process;

I forgot to mention I will need to change the duty of the output. I'm new to modelsim, May I know how do I create the correct test bench?

A testbench is another VHDL file that you write in the same way as any other VHDL. But you can use non-synthesisable and behavioural parts that you cannot use for synthesis. eg - generating a clock:

You did not tell which problem you observe. How do you know that there's an error in your code?

process(clk)
begin
  if rising_edge(clk) then
    if en = '1' then    --only high once every 50 clocks
      --logic with 1/50 clock
    end if;
  end if;
end process;

It doesnt output a clock. It uses an enable to only enable the logic inside the process once every N clocks (depending on how often you set the enable high). It does the same job as a 1/50 clock, but much more safely.