Forum Discussion
Altera_Forum
Honored Contributor
12 years agoA ripple clock is a clock that is generated via logic - ie. exactly what you have done - used a counter to create a slower clock from a faster one. It is better practice to use the same clock over the whole system and generate clock enables to only enable the target at the given rate. So to divide a clock by 50, you create an enable signal that is high for 1 clock cycle in 50:
process(clk)
begin
if rising_edge(clk) then
if en = '1' then --only high once every 50 clocks
--logic with 1/50 clock
end if;
end if;
end process;
Another question - have you created a testbench to test this code in the simulator before you go to the hardware (it will make your life easier)