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Altera_Forum's avatar
Altera_Forum
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12 years ago

cant find the problem with my code

Hi everyone, i am using DE0-nano cyclone IV E. Basically im using the LEDs to signal whether i have over counted. I do not know what is wrong but my integer range doesn't seem to limit the count, and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

A testbench is another VHDL file that you write in the same way as any other VHDL. But you can use non-synthesisable and behavioural parts that you cannot use for synthesis. eg - generating a clock:

signal clk : std_logic := '0';

clk <= not clk after 10ns; --50 MHz clock.