New Contributor
New ContributorI'm posting some screen shots showing what I'm seeing. These images show searching for rom2 in the timing analyzer and in the Quartus node finder. Note that rom2 appears in the node finder but not in the timing analyzer.
Super ContributorTry turning on the Hierarchical option in the Name Finder. Without that, wildcards only search the current hierarchical level you've specified (you'd have to do something like *|*|* etc. to search further down). It looks like that 3rd ROM might be further down in the hierarchy.
New ContributorWith Hierarchical on, Compatibility mode gets turned off and wild cards don't work. But if I clear the filter and select get_pins it seems to list all pins in the design in alphabetical order. Still no rom2.
In any case, all 3 ROMs are in the same Verilog module and therefore should be at the same hierarchical level.
Super ContributorWildcards don't work? I've never had that issue with hierarchical. Wildcards are the main point behind that option, so I'm not sure why it's not working for you. What exactly happens when you use a wildcard?
The only other thing I can think of is an issue with the timing netlist. Try deleting and recreating the timing netlist manually in the Timing Analyzer. You might even want to try a full recompile of the design. It doesn't make sense that a whole bunch of nets are visible in tools like the Tech Map Viewer (Node Finder) and not in the Timing Analyzer (Name Finder).
New ContributorIn the Name Finder Hierarchical and Compatibility Mode are mutually exclusive, one or the other is always checked but not both. With Hierarchical checked wildcards don't work, it finds nothing if there is anything other than one *.
I deleted everything in the project, databases, etc., just left the source files, qip files and the qpf and qsf files. Recompiled and rom2 still isn't seen by the timing analyzer.
The reason this is a problem is because all 3 ROMs need multicycle timing constraints. I can't add the multicycle constraint for rom2 because the timing analyzer thinks it doesn't exist. So I don't know if the design is being properly analyzed or constrained. If a major piece of the design isn't being analyzed then the compiled results can't be relied on to be correct.
