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Altera_Forum's avatar
Altera_Forum
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15 years ago

cannot write PCIE interrupt status register

Hi,

I am working at Quartus 10 SP3, the device is A2GX65,when i using SOPC to building a pcie system,some problem about interrupt is occured.

I write to P2A_MAILBOX registers from NIOS, and I found the coresponding P2A_MAILBOX_INT bit is asserted.

But when I write 0x0 to pcie_p2a_interrupt_status_reg to clear the IRQ, it didn't change.

Does anyone know why?

regards.

--xcq

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi,

    this is a RW1C (read/write '1' to clear) register. You have to write a '1' to the status bit you want to clear.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Hi,

    this is a RW1C (read/write '1' to clear) register. You have to write a '1' to the status bit you want to clear.

    --- Quote End ---

    Thanks very much.

    I've fixed it out.