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Altera_Forum's avatar
Altera_Forum
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9 years ago

Cannot the parameters list be empty in SystemVerilog?

Hi All, What's the problem with the following code? pmu# () i_pmu (// Outputs .clk0 (clk_mn), // Inputs .rstn_ext (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Quartus doesn't tolerate empty parameter lists, no.

Cheers,

Alex