cannot simulate PLL ip

Hi,

I try to use a PLL in my design. I successfully create it from Qsys.

Then i compile the files needed for simulation ( a vhd 'top level' file and a file called uart_pll_altera_iopll_151_m22pvxi.vo compiled in its own library).

When i try to simulate the design Modelsim-Altera complains about the uart_pll_altera_iopll_151_m22pvxi.vo file like this :

.....

uart_pll_altera_iopll_151_m22pvxi.vo(137): Instantiation of 'altera_pll' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /uart_pll/iopll_0

File: ../uart_pll/altera_iopll_151/sim/uart_pll_altera_iopll_151_m22pvxi.vo# Searched libraries:# ../uart_pll_altera_iopll_151

...

it looks like the generated file from quartus calls another component which canot be found....

anybody knows how to deal with it? should i include any primitive library ?