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CZHE0's avatar
CZHE0
Icon for New Contributor rankNew Contributor
7 years ago

Cannot see internal signals in ModelSim

I'm launching my verilog testbench through Quartus 18.1.0 (Tools -> Run Simulation Tool -> RTL Simulation), which opens up ModelSim 10.5b SE. I go through the following steps: 1) Compile my testbenc...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Colin,

Okay,

  1. Try by deleting the work folder and disabling optimization option in the ModelSim compilation option. (disable in both Verilog and VHDL tab).
  2. Also try by add VoptFlow = 0 in modelsim.ini.

we can see all the signals in the wave window by selecting all items in the design.

If still, you can't see internal signals. I recommend that you ask in the Mentor Forum.

Regards

Anand