Cannot run stimulus module using Quartus Prime?

Attempting to learn Verilog right now. I am currently running through Verilog HDL by Palanatkir and am using Quartus Prime Lite as my current EDA. I am very new at this but just wondering, the book has us code a stimulus block as one of our very first exercises. I cannot figure out how to get Quartus to compile with it, as Quartus just states that the top level block has no logic.

        module stimulus;
        reg clk;
        reg reset;
        wire  q;
        
        R_CC rcc0(q, clk, reset);
        
        initial
            clk = 1'b0; // set clk to 0
        always
           # 5 clk = ~clk; // toggle clk every 5 tu
            
        initial
        begin
            reset = 1'b1;
           # 15 reset = 1'b0;
           # 180 reset = 1'b1;
           # 10 reset = 1'b0;
           # 20 $finish; // terminate sim
        end
        
        initial
            $monitor($time, " Output q = %d", q);
            
    endmodule
    // module - basic building block of Verilog
    // Ripple Carry Counter
    module R_CC(q, clk, reset);
        output  q; // io signal and vector decl
        input clk, reset;
        
        T_FF tff0(q, clk, reset);
        T_FF tff1(q, q, reset);
        T_FF tff2(q, q, reset);
        T_FF tff3(q, q, reset);
        
    endmodule
    module T_FF (q, clk, reset);
        output q;
        input clk, reset;
        wire d;
        
        D_FF dff0(q, d, clk, reset);
        not nl(d, q); // not is a Verilog primative
        
    endmodule
    module D_FF(q, d, clk, reset);
        output q;
        input d, clk, reset;
        reg q; // wtf
        
        always @(posedge reset or negedge clk)
        if (reset)
            q <= 1'b0;
        else
            q <= d;
            
    endmodule