Cannot run stimulus module using Quartus Prime?

RTL that you can implement in the FPGA needs to be "synthesizable" So in the code above things like# and $monitor do not map to hardware resources that are inside the FPGA and are provided in the language for the reasons Tricky said. If you google "synthesizable verilog" you'll find a lot of topics on this to help you identify what parts are synthesizable and which are simulation only. In Quartus there are a bunch of templates you can refer to which should all be synthesizable, with a verilog file open in Quartus go to Edit --> Insert Template and navigate to the verilog templates to see examples of how you code various synthesizable blocks.