Cannnot insert breakpoints

Hi.. an Altera newbie here. I'm working with Quartus II 10sp1 & Modelsim Altera 6.5e. I have a very simple muxing program which redirects one of the two input UART ports to an output UART post based on a switch signal.

When I run the simulation, I cannot set breakpoints in my actual code; only in the testbench file and maxii-atoms.v. As a result I cannot see how the testbench signals propagate through my code.

I ran the same code on a competitor's simulator (which I'm used to) & it runs fine and the results differ big time from Altera's.

help please!

Thanks

The actual code:

module e1188_try (

//UART1

output reg uart1_rx,

input uart1_tx,

output reg uart1_cts,

input uart1_rts,

//UART2

output reg uart2_rx,

input uart2_tx,

output reg uart2_cts,

input uart2_rts,

//Output UART interfaces

//UARTX

input wire uartx_rx,

output reg uartx_tx,

input wire uartx_cts,

output reg uartx_rts,

//control

input uart_switch_n //1 -> uart1, 0 -> uart2

);

always @ (uart_switch_n or uart1_tx or uart1_rts or uart2_tx or uart2_rts or uartx_rx or uartx_cts)

begin

if (uart_switch_n)

begin

uartx_tx = uart1_tx;

uart1_rx = uartx_rx;

uartx_rts = uart1_rts;

uart1_cts = uartx_cts;

end

else

begin

uartx_tx = uart2_tx;

uart2_rx = uartx_rx;

uartx_rts = uart2_rts;

uart2_cts = uartx_cts;

end

end

endmodule

---------------------------------------------------

Test bench:

module e1188_try_tb;

//UART1

//output reg uart1_rx,

//output reg uart1_cts,

reg uart1_tx;

reg uart1_rts;

//UART2

//output reg uart2_rx,

//output reg uart2_cts,

reg uart2_tx;

reg uart2_rts;

e1188_try tb(

uart1_rx,

uart1_tx,

uart1_cts,

uart1_rts,

uart2_rx,

uart2_tx,

uart2_cts,

uart2_rts,

uartx_rx,

uartx_tx,

uartx_cts,

uartx_rts,

//control

uart_switch_in //1 -> uart1, 0 -> uart2

);

//Output UART interfaces

//UARTX

/*

input wire uartx_rx,

output reg uartx_tx,

input wire uartx_cts,

output reg uartx_rts,

*/

//control

reg uart_switch_n; //1 -> uart1, 0 -> uart2

assign uart_switch_in = uart_switch_n;

initial

begin

uart_switch_n = 1'b0;

uart1_tx = 1'b0;

uart1_rts = 1'b1;

uart2_tx = 1'b0;

uart2_rts = 1'b1;

end

initial

begin

forever# 20000 uart_switch_n = ~uart_switch_n;

end

initial

begin

forever# 25 uart1_tx = ~uart1_tx;

end

initial

begin

forever# 50 uart1_rts = ~uart1_rts;

end

initial

begin

forever# 15 uart2_tx = ~uart2_tx;

end

initial

begin

forever# 75 uart2_rts = ~uart2_rts;

end

endmodule