Can you synthesize your design in a specific order?

You want to investigate the Quartus Design Explorer and the feature called Logiclock Regions. Basically it allows you to define a region (usually rectangular but does not have to be) and constraint particular logic to be placed into that region. This allows you to optimize the placement and routing on that module of logic.

Some help info: https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/optimize/lock/flp_view_logiclock_reg.htm

If you want to close timing, I don't think synthesize your design in specific order will help. Instead, I recommend to checkout the application notes below:

https://www.intel.com/content/www/us/en/docs/programmable/683145/21-3/an-584-timing-closure-methodology-for.html#dropdown-1-0

https://www.intel.com/content/www/us/en/docs/programmable/683664/19-3/an-903-accelerating-timing-closure-in.html

Better than Logic Lock for this would be incremental compilation (in the Standard edition; called block-based compilation in Pro). Set the critical part of your design as a design partition. Compile your design and make sure that the design partition is meeting timing. If it is, you then "lock down" the critical partition so that it is not changed in future recompilations. You can then continue to work on the rest of the non-critical parts of the design.

You can do this along with Logic Lock, but LL restricts the placement options the Fitter has.

You don't mention if you are using standard or Pro, but here are trainings on this (with links to documentation):

https://learning.intel.com/developer/learn/course/external/view/elearning/202/introduction-to-incremental-compilation-in-the-intelr-quartusr-prime-standard-edition-software

https://learning.intel.com/developer/learn/course/external/view/elearning/250/incremental-block-based-compilation-in-the-intel-quartusr-prime-pro-software-introduction

https://www.intel.com/content/www/us/en/programmable/documentation/yrh1513988099640.html

Good to know. Thanks for the resources!

Oh this is perfect. I was concerned about the fitter restrictions with Logic Lock and the courses I found were all for Pro and I use standard.

Thanks!

I’m believe that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan