can we have the internal simulator back please

I support this request for 200%!

I have been using the internal simulator since day 1. It is a perfect thing to test small building blocks.

Can someone start a poll on this?

I think you'll find that as 99% of altera's customer base have no need for the internal simulator, it makes no financial sense to continue supporting it.

You could always set up the testbench and entity layout for them in HDL, so all they need to do is fill in the logic and run a TCL script to see what their design is doing.

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Can someone start a poll on this?

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You're welcome ;-) http://www.alteraforum.com/forum/showthread.php?t=24415 (http://www.alteraforum.com/forum/showthread.php?t=24415)

BTW: You could have done this yourself, setting up such a poll is really easy.

Personally, I also liked to simulator for testing small entities, it was faster for me then writing a testbench for ModelSim.

I've always been a fan of the simulator too.

Note that in Q10.0 the GUI was re-written, so carrying the simulator forward would have been a very large project(it's not like they just dropped it for fun). Also, since it's not a generic simulator, the underlying models have to be hand-created for each device. So as new families like Straix V come out, their simulations have to be re-created.

Now, I think they could have dropped simulation support for large families like Stratix V, since it really wasn't good enough for anything of that size, but CPLDs, Cyclone designs, or just quick sanity checks, it was really nice.

One other option I've seen, if you don't want users to deal with an RTL testbench, is using Tcl to drive Modelsim. For people who think that way, it's really quite straightforward. I don't have a good example on hand, but it's literally a line to drive a signal. Just a thought as something easy.

They already dropped simulation for Stratix V in Q9.1.

I don't have any experience with ModelSim (going back to the 80ties where a pencil drawn timing diagram is all what the smaller companies had to do PAL/EPLD design) but I wonder if you can do something simple as:

generate a file for say a Stratix II GX, do a simulation to see what comes out on the TX line of a GX-transceiver, copy the waveform on to the RX signal, and then simulate again. It was very easy to shift the reset, alignment request pulses and see how it behaved.

Incidently they also dropped support for some FLEX devices in Q9.1 also, so I will end up with 3 versions of QII on my system :9.0sp2 for Flex, 9.1sp for the Cyclone IV starterkit and as the last with the simulator, and Q10.0 (where we have to do as Xilinx (pardon my French) users do ...)

Using an external simulator is not really the issue I believe, it is rather the loss of the waveform editing that hurts us.

Driving Modelsim with Tcl (or some other script language?) may be interesting. Can you give a good example?

Stratix V wasn't in Q9.1. Do you mean Stratix IV? My feeling is that a transceiver really shouldn't be simulated with Altera's simulator. Just too large/long of a design to get going. Personally, I hate the simulator for anything complex at all, because cutting/copying/modifying waveforms is such a pain. But I did think it was great for throwing down a small piece of logic and seeing what happens under some specific set of conditions. I would like to see a better document from Altera(of have someone point one out if it exists) on how to get a simulation running in ModelSim-Altera Edition in less than 5 minutes. If I could do that, I would be happy.

I had a Tcl example from many years ago but can't find it. I think at it's most basic, you use force and run, i.e.:

force /system/clk 1

run 10ns

force /system/clk 0

run 10ns

(I may have the synax incorrect.) Most likely you'll do a process for the clock, like so:

proc run_cycles {"num_cycles 1"} {

for {set i 0} {$i < $num_cycles} {incr i} {

force /system/clk 1

run 5ns

force /system/clk 0

run 5ns

}

}

(Again, I'm just typing here, so maybe incorrect)

With that setup, you can the do stuff like:

force /system/ina 1

force /system/inb 0

force /system/inc 0

run_cycles 10 ;# Runs for 10 clock cyles

<insert new force statements here>

Again, just doing it on the fly. I am certain Tcl is NOT the way to do a comprehensive testbench. It's going to be slow, it's not going to have the capabilities of a testbench, and it's not synthesizable. That being said, as a teaching tool or a quick way to get started, it can be pretty easy. (Note that Verilog and probably VHDL have similar "sequential" commands. You still have to create a testbench. It's pretty trivial, but for a teaching environment would still probably take a day...)