Honored Contributor
Honored ContributorStratix V wasn't in Q9.1. Do you mean Stratix IV? My feeling is that a transceiver really shouldn't be simulated with Altera's simulator. Just too large/long of a design to get going. Personally, I hate the simulator for anything complex at all, because cutting/copying/modifying waveforms is such a pain. But I did think it was great for throwing down a small piece of logic and seeing what happens under some specific set of conditions. I would like to see a better document from Altera(of have someone point one out if it exists) on how to get a simulation running in ModelSim-Altera Edition in less than 5 minutes. If I could do that, I would be happy.
I had a Tcl example from many years ago but can't find it. I think at it's most basic, you use force and run, i.e.: force /system/clk 1 run 10ns force /system/clk 0 run 10ns (I may have the synax incorrect.) Most likely you'll do a process for the clock, like so: proc run_cycles {"num_cycles 1"} { for {set i 0} {$i < $num_cycles} {incr i} { force /system/clk 1 run 5ns force /system/clk 0 run 5ns } } (Again, I'm just typing here, so maybe incorrect) With that setup, you can the do stuff like: force /system/ina 1 force /system/inb 0 force /system/inc 0 run_cycles 10 ;# Runs for 10 clock cyles <insert new force statements here> Again, just doing it on the fly. I am certain Tcl is NOT the way to do a comprehensive testbench. It's going to be slow, it's not going to have the capabilities of a testbench, and it's not synthesizable. That being said, as a teaching tool or a quick way to get started, it can be pretty easy. (Note that Verilog and probably VHDL have similar "sequential" commands. You still have to create a testbench. It's pretty trivial, but for a teaching environment would still probably take a day...)
