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JRamo9's avatar
JRamo9
Icon for New Contributor rankNew Contributor
7 years ago

Can someone please help me. I cant seem to figure out what is causing this error: Error (10500): VHDL syntax error at mult_control_ex.vhd(58) near text "END"; expecting "begin", or a declaration statement

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity mult_control is port( clk, reset_a, start : in std_logic; count : in unsigned (1 DOWNTO 0); input_s...
SAR's avatar
SAR
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

HI,

First of all you can maintain some coding standards or at least by giving spacing /Tab which will help in eliminating many errors.

I can see many syntax error few are listed below

Statements Syntax error

  • -architecture logic of mult_control is -> -
  • if reset_a = '1' ; then -> ;
  • else rising_edge(clk) then -> else or elsif
  • architecture is not ended. ->No architecture logic;
  • few Conditional Control are missing end statements by having spacing/Tab we can eliminate such.