Can someone please help me. I cant seem to figure out what is causing this error: Error (10500): VHDL syntax error at mult_control_ex.vhd(58) near text "END"; expecting "begin", or a declaration statement

HI,

First of all you can maintain some coding standards or at least by giving spacing /Tab which will help in eliminating many errors.

I can see many syntax error few are listed below

Statements Syntax error

• -architecture logic of mult_control is -> -
• if reset_a = '1' ; then -> ;
• else rising_edge(clk) then -> else or elsif
• architecture is not ended. ->No architecture logic;
• few Conditional Control are missing end statements by having spacing/Tab we can eliminate such.

Hi JRamo9,

Kindly check if the functionality of the edited version is correct

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity mult_control is port(

clk, reset_a, start : in std_logic;

count : in unsigned (1 DOWNTO 0);

input_sel, shift_sel : out unsigned(1 DOWNTO 0);

state_out : out unsigned(2 DOWNTO 0);

done, clk_ena, sclr_n : out std_logic

);

end mult_control;

architecture logic of mult_control is

type state_type is (idle, lsb, mid, msb, calc_done, err);

signal current_state: state_type;

signal next_state: state_type;

begin

process (clk, reset_a) begin

if reset_a = '1' then

current_state <= idle;

elsif rising_edge(clk) then

current_state <= next_state;

end if;

end process;

process (current_state, start, count) begin

case current_state is

when idle =>

if start = '1' then

next_state <= lsb;

else

next_state <= idle;

end if;

when lsb =>

if start = '0' then

if (count = "00") then

next_state <= mid;

else

next_state <= err;

end if;

end if;

when mid =>

if start = '0' then

if (count = "01") then

next_state <= mid;

elsif (count = "10") then

next_state <= msb;

else

next_state <= err;

end if;

end if;

when msb =>

if start = '0' then

if (count = "11") then

next_state <= calc_done;

else

next_state <= err;

end if;

end if;

when calc_done =>

if start = '0' then

next_state <= idle;

else

next_state <= err;

end if;

when err =>

if start = '0' then

next_state <= err;

else

next_state <= lsb;

end if;

end case;

end process;

end logic;

Thanks