can someone help on this

Hi Tricky, i have tried to fix the locked and unlocked states, see how the code looks, hope i am on the right track? i am an amateur in vhdl

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity uppgift_dorr is

port( clk : in std_logic; --clock signal

reset : in std_logic; --reset signal

key_0, key_1, key_2, key_3 : in std_logic;

LEDR : out std_logic_vector (1 downto 0); -- Output LEDR

LEDG : out std_logic_vector (1 downto 0) -- Output LEDR

);

end uppgift_dorr;

architecture Behavioral of uppgift_dorr is

--Defines the type for states in the state machine

type state_type is (closed,opened,locked,unlocked);

--Declare the signal with the corresponding state type.

signal Current_State, Next_State : state_type;

begin

-- Synchronous Process

process(clk, reset)

begin

if( reset = '1' ) then --Synchronous Reset

Current_State <= closed;

elsif (rising_edge(clk)) then --Rising edge of Clock

Current_State <= Next_State;

end if;

end process;

-- Combinational Process

Process(Current_State, key_0, key_1, key_2, key_3)

begin

LEDG <= "00"; LEDR <= "00";

case Current_State is

when closed =>

if ( key_0 = '1' ) then

Next_State <= closed;

LEDG <= "00"; LEDR <= "00";

else

Next_State <= opened;

LEDG <= "01"; LEDR <= "01";

end if;

when opened =>

if ( key_1 = '1' ) then

Next_State <= opened;

LEDG <= "01"; LEDR <= "01";

else

Next_State <= closed;

LEDG <= "11"; LEDR <= "10";

end if;

when locked =>

if ( key_2 = '1' ) then

Next_State <= locked ;

LEDG <= "11"; LEDR <= "11";

else

Next_State <= opened;

LEDG <= "10"; LEDR <= "00";

end if;

when unlocked =>

if (key_3 = '1' ) then

Next_State <= unlocked;

LEDG <= "11"; LEDR <= "11";

else

Next_State <= closed;

LEDG <= "10"; LEDR <= "10";

end if;

end case;

end process;

end Behavioral;