Can Quartus Prime 16 detect changes in sources to show the build is out of date?

Hello Sstrell,

The design changes are being implemented. I can see them in the behavior of the FPGA when I load a new design. This isn't a bug in compiling. It's just an annoyance that the Quartus GUI doesn't seem to track changes and mark the design out of date. I would expect to get the message I'm seeing only if the design hasn't changed since the last time it was successfully compiled. What I actually see (Again this is in Quartus 16.0) is that whether or not I made a change, Quartus will compile the design again without the warning message if I have closed and re-opened the project. It will always give the warning, whether or not I make design changes, after running compile design once in the current session.

Regards,

Gabor