Forum Discussion
Altera_Forum
Honored Contributor
15 years agoDid you try using a + sign? I don't know how you did a ripple-carry adder but I'm guessing it might have been too low-level for synthesis to understand your intent. Just a guess. Also, open your verilog in Quartus and go to Edit -> Insert Template -> Verilog -> Full Designs -> Arithmetic. These should all get optimal synthesis(i.e. carry chain).
I haven't seen anyone manually instantiate carry_sum in many years.