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ScottHu2021's avatar
ScottHu2021
Icon for New Contributor rankNew Contributor
4 years ago

Can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP"

Hi , I can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP - Intel Communities" any more. Anybody can help me? Thanks, Scott
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Scott,


I can see the timing issues in the design.

The issues are not located inside the EMIF but within the IP.

Maybe you can relocate the pll to closer location to the EMIF IP.

Also you can run the compilation with the High Effort and maybe try with different seed.


It's not much I can help you in term of this.

The timing specialist can help you to close the timing.


Thanks,

Adzim