Can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP"

Hi Adzim,

With the configuration "PLL reference clock's frequency: 100M and the 50M clock connection to the pll_ref_clk", the device can connect to the External Memory Interface Toolkit and finish the calibration procedure. But with the configuration "PLL reference clock's frequency: 50M", the device can not connected to the toolkit.

Would you like to compile the project attached in this post? It is a very simple project to initialize a DDR3 controller and performs data write and read and then compare the data readback with the last write value. The PLL reference clock frequency is configured as 50M.

Even with this simple implementation, there are still some timing violations with the DDR3 controller. With my poor experience, I do not know how to fix these timing issues. Would you like to give some hints?

Thanks and happy new year too!

Scott