Can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP"

Hi Adzim,

The DDR3 test project was updated,

If we set the PLL reference clock 's frequency to 50M and connect the external 50M clock to the pll_ref_clk, the test failed.

if we set the PLL reference clock's frequency to 100M and connect the external 50M clock to the pll_ref_clk, the test passed ( the write data equals to the data read back).

Please refer to the attached project archive.

Thanks,

Scott.