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ScottHu2021's avatar
ScottHu2021
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4 years ago

Can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP"

Hi , I can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP - Intel Communities" any more. Anybody can help me? Thanks, Scott
AdzimZM_Altera's avatar
AdzimZM_Altera
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4 years ago

Hi Scott,


Thank you for the updates.


I'm not clear about the DDR3 is not working with the 300M frequency.

The timing report looks okay and the memory is passing the calibration like you said.


But maybe for now you can test the design with only the EMIF IP to see if the memory interface can work or not.


Regards,

Adzim


  • ScottHu2021's avatar
    ScottHu2021
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Adzim,

    I create a small project dedicated to test the DDR3. Please refer to the attached project archive.

    In this project, 50M clock is used as the pll_ref_clock of ddr controller , and a derived 100M clock will drive the logic which reads/ writes DDR.

    After programming the FPGA, I can not monitor the assert of the signal "local_cal_success". May you give me some hints about this problem?

    Thanks!

    Scott