Can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP"

Hi Adzim,

Currently, we have changed the hardware a little bit, that it, add a 50M oscillator and assign its' output to one pin of DQ I/O bank as our discussed before. Unfortunately, the DDR3 still can not work with 300M frequency.

The timing report of DDR controller is as following:

Initializing DDR database for CORE ddrc_p0
Finding port-to-pin mapping for CORE: ddrc_p0 INSTANCE: ddrc_u|ddrc_inst
Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.461
Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.303
Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 11.060
Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.834
Core: ddrc_p0 - Instance: ddrc_u|ddrc_inst
setup hold
Address Command (Slow 1100mV 85C Model) | 0.975 0.968
Bus Turnaround Time (Slow 1100mV 85C Model) | 5.512 --
Core (Slow 1100mV 85C Model) | 1.461 0.303
Core Recovery/Removal (Slow 1100mV 85C Model) | 11.06 0.834
DQS vs CK (Slow 1100mV 85C Model) | 0.45 0.562
Postamble (Slow 1100mV 85C Model) | 0.817 0.817
Read Capture (Slow 1100mV 85C Model) | 0.315 0.268
Write (Slow 1100mV 85C Model) | 0.366 0.366

we also monitored the signal "local_cal_success" exported from the controller interface together with the "local_init_done" , which are all high after power-on. So, the calibration and initialization process should succeeded.

BTW, in the "report top failing paths", there are some setup slack violations of NIOS address and data bus ( in our design, there is a NIOS implemented ), I am not sure if these timing violations will affect the DDR operation.

Regards,

Scott