Occasional ContributorCan I write, compile and simulate VHDL code by using only modelSim?
I just started learning using Quartus Prime Standard and I find it taking too much time each time I want to modify the VHDL code in Quartus ,then compile then simulate using the modelSim.
is there a possibility of Using only in the development phase the ModelSim while I can modify the TestBench and the Source code on the same window?
Unless you're doing a gate-level simulation that requires device timing delays, you don't need to compile in Quartus at all before running a simulation in ModelSim. Quartus can generate simulation scripts for you (for compiling in Modelsim, setting up the waveform view, etc.), but you don't even need to do that.
At a minimum, you might want to run Analysis & Elaboration in Quartus to verify syntax and connectivity, but other than that, you don't need to compile any further before simulating.
