Can EDIF Instantiated Entity be Defined by Subdesign During Compile?

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... Altera primitive functions...

An Altera T-Flip Flop does not have ports for VDD, GND, CB, R(active high), or QB. The additional functions would have to be defined in a subdesign or module.

Can a subdesign defined in terms of Altera functions be used during compilation to define an entity in the EDIF netlist?

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I wouldn't try to find an Altera primitive that corresponds to the thing in the EDIF file. I'd use a simple HDL file with an RTL description written in a standard style that will synthesize D flip flops. (The actual registers in the device are D flip flops.)