Calculating width of input port in Verilog module

No,

I found a workaround which works for my case. Since i do not strictly need the port with dynamic width at the very top i hid it in another verilog file. That way i implemented all the logic and width calculations in verilog and then wrapped it in another block design file which doesn't have the dynamic width port exposed. Its ports are all derived straight-forward from the parameters and the ports with the width calculated at compile time are all hidden within verilog.

Nevertheless I would still like to know if it's possible since this workaround only works if the dynamic port does not need to be exposed.