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HerrNamenlos123
New Contributor
New ContributorCalculating width of input port in Verilog module
I want to create a Verilog module which can be parameterized, but the width of the input port must be calculated at compile time. I'm using Intel Quartus Prime Lite 20.1.
I want it to be exactly li...
SyafieqS
Super Contributor
Super ContributorHerr,
Are you able to work on this?
- HerrNamenlos123
No,
I found a workaround which works for my case. Since i do not strictly need the port with dynamic width at the very top i hid it in another verilog file. That way i implemented all the logic and width calculations in verilog and then wrapped it in another block design file which doesn't have the dynamic width port exposed. Its ports are all derived straight-forward from the parameters and the ports with the width calculated at compile time are all hidden within verilog.
Nevertheless I would still like to know if it's possible since this workaround only works if the dynamic port does not need to be exposed.
