cache controller and read-during-write behavior

Something else I've discovered.

There is a 1 clock stall when a read from tightly coupled data memory immediately follows a write to the same memory block.

Basically the write cycle can only be done when it is actually required - and the decision takes a clock.

The read is done unconditionally - ie regardless of the opcode byte or the actual memory block referenced by the high-order address bits.

The same delay may affect data cache operations.