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Altera_Forum's avatar
Altera_Forum
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13 years ago

cache controller and read-during-write behavior

Hello all, I'm in the process of writing a simple cache controller. I want this controller to exhibit write-back behavior, i.e. when the cache is being written to by the processor, the control...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

That is what I expected, as the following code indicates:

wr_addr_int <= to_integer(unsigned(wr_addr));

rd_addr_int <= to_integer(unsigned(rd_addr));

process(clk)

begin

if rising_edge(clk) then

if we = '1' then

for i in 0 to DATA_BYTE_WIDTH-1 loop

ram(wr_addr_int)(i) <= data(8*(i+1)-1 downto 8*i);

end loop;

end if;

q_int <= ram(rd_addr_int);

end if;

end process;

UNPACK : for i in 0 to DATA_BYTE_WIDTH-1 generate

q(8*(i+1)-1 downto 8*i) <= q_int(i);

end generate;

Thank you for verifying that for me, I'm just about ready to start my verificiation efforts.