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Altera_Forum
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13 years ago

cache controller and read-during-write behavior

Hello all, I'm in the process of writing a simple cache controller. I want this controller to exhibit write-back behavior, i.e. when the cache is being written to by the processor, the control...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I've just been looking at some signaltap traces of bus cycles for M9K on ArriaII.

With 'OLD_DATA' enabled (and single clock) during a write on s1, s1 returns the old data, but s2 returns the new data.

So to read the old data during a write you'd need to put the write address onto both the s1 and s2 address inputs.

This might be what you've already discovered.