Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

cache controller and read-during-write behavior

Hello all, I'm in the process of writing a simple cache controller. I want this controller to exhibit write-back behavior, i.e. when the cache is being written to by the processor, the control...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You are probably getting a random mix of old and new values for each bit. The timings might be such that the new value always wins!

I guess reads aren't a problem - you can just discard the data.

For writes you may have to add a 'store buffer' so they can be processes asynchonously (and pipelined).