Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi,
Only one process should generate "motor_state" but you get "motor_state <= stop;" in your 2nd process ! It seems you are new to VHDL, I suggest you to first describe completely your finite state machine by a schema : inputs and transitions to select which state, outputs for each state. and then simply transcode to VHDL.look for "moore machine", "mealy machine".
more secure like this.
else you will spend hours and get headache to "debug" a bad conception. EDIT : "Multiple drivers" means that tour "motor_state" is driven by more than one source and the synthesizer don't know how to resolve this signal, beacause this signal is declared as unresolved. "Unresolved signal" declaration is a good thing to early catch this error.