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Altera_Forum
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14 years ago

Bus or IOs skew management issue

Hello dears: As a example, a internal resgister fans out 22 signals to 22 pins. Can I ensure these 22 path getting fix delay? If can, how to get it? The jitter requirement is below 1ns, as smal...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Got it, but I don't know the intricacies(such as if the delays vary over PVT, does it matter, or is it fine if they all vary together)? Anyway, if you're driving out from a flip-flop, the best method is to use the output flip-flops in the I/O cell. General routing delays in the FPGA will be more subject to variaion, where the global clock tree is designed for low-skew(and jitter should be low).