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Altera_Forum
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14 years ago

Bus or IOs skew management issue

Hello dears: As a example, a internal resgister fans out 22 signals to 22 pins. Can I ensure these 22 path getting fix delay? If can, how to get it? The jitter requirement is below 1ns, as smal...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hello Rysc:

My case is of spercial application.

I will use FPGA to generate a signal which feeds TDC chips. Then if there are hundreds of ps timing variation would be an issue for my case. That's why i need the route inside FPGA of this signal to be fixed like PCB trace.

I hope that i have explained my question clearly.

Thanks