Bus or IOs skew management issue

Hello Cris72&Rysc:

Thanks for your help!

In fact, I'd like the 22 paths have fix propagation time from inside FPGA to another deivce. It's will be ok whether there are skew on these 22 paths or not.

But, each path's jitter must be very small, blow 1ns would be ok for my case.

I think there is would be issue since there are jitters among diff IOEs. I can't find any information about this jitter in Altera's datasheet.

For one path, there are 2 section, one is inside FPGA, another is outside the FPGA (which is pcb trace - fix prop time). What't i want is how to fix the propagation time inside FPGA include the IOE propagating time?

Thanks