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Altera_Forum
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14 years ago

Bus or IOs skew management issue

Hello dears: As a example, a internal resgister fans out 22 signals to 22 pins. Can I ensure these 22 path getting fix delay? If can, how to get it? The jitter requirement is below 1ns, as smal...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Replicate the output register 22 times(either manually or with assignment) so the I/O output register can be used and it will be fed by a global clock tree. I wrote the following document that might help(it's a different topic, but somewhat related)

http://www.alterawiki.com/wiki/register_duplication_for_timing_closure

That will give you the least amount of skew, and much better than trying to get the router to add/subtract delays to get minimally skew to 22 locations.