Altera_ForumHonored Contributor14 years agoBus or IOs skew management issue Hello dears: As a example, a internal resgister fans out 22 signals to 22 pins. Can I ensure these 22 path getting fix delay? If can, how to get it? The jitter requirement is below 1ns, as smal...Show More
Altera_ForumHonored Contributor14 years agoIf possible, CPLD is better for me, if not, FPGA is also OK.
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